This paper presents a novel approach to obtain fast locking PLL by embedding a nonlinear element in the loop of PLL. The nonlinear element has a general parametric Taylor expansion. Using genetic algorithm (GA) we try to optimize the nonlinear element parameters. Embedding optimized nonlinear element in the loop shows enhancements in speed and stability of PLL. To evaluate the performance of the proposed structure, various tests performed and results compared with standard phase locked loop. The tests and results show the superior performance of the proposed PLL.

Now days, sharing data in communication systems and computers require high levels of Information security. Side channel attack is one of the methods which it is applied to attack cryptographic systems such as smart cards. In this paper, a new approach for countermeasuring cryptographic algorithms has been proposed and implemented on FPGA. The scheme is based on using Phase Locked Loop in AES algorithm which by disturbing power consumption pattern and execution time of different rounds, the resistance of the algorithm against power attack has been increased. Masking and hiding technique has been used to protect the encryption key. Overall, the proposed method has been simulated within TSMC 65nm technology platform and outstanding success has been obtained; in applying the technique to AES, the overhead was 13% in CMOS area, 15% in power consumption, 2% decrease in working frequency while finding the key became difficult for attackers. In addition, the proposed method has been implemented on FPGA and satisfactory results have been obtained for an acceptable number of samples of the power trace.

Single-phase voltage source inverters (SP-VSIs) are widely used in grid connected solar photovoltaic (PV) systems. This paper deals with the dynamic modeling and stability analysis of single-phase grid connected PV inverters taking the PLL dynamics into account. The PLL structure employed in this paper includes two control branches; the main branch, known as phase estimation loop, extracts the phase and frequency of the grid voltage and the other branch, known as voltage peak estimation loop, determines the grid voltage amplitude. In this way, the paper first proposes design considerations for the dc-link voltage control and PLL control loops. Then, unified dynamic modeling of the SP-VSI system comprising PLL, dc-link dynamics and grid is presented and linearized block diagram of the whole system is extracted. The linearized block diagram depicts the interaction between the control loops of the PLL and dc-link system, where the PLL control loops consist of phase/frequency and amplitude estimation loops of the grid voltage. Next, the small signal stability of the full system is presented, and impacts of grid strength, operating point, and PLL closed loop bandwidth on the performance of SP-VSI are investigated by the modal analysis and time domain simulations.

Phase, frequency, and amplitude of grid voltage are important information in grid-connected photovoltaic systems. For proper and stable operation of a system, a fast and correct estimation of grid information under grid variations and disturbances is very crucial. In this paper, an adaptive phase-locked loop (PLL) structure is proposed which tracks the phase jumps of grid voltage fast and smoothly. If a jump occurs in grid voltage phase transient state at the frequency estimation of frequency lock loop (FLL) will be almost zero. The settling times of the estimated phase, frequency, and amplitude of the proposed PLL are also slightly low. The proposed PLL consists of the second-order generalized integrator (SOGI) and frequency locked loop (FLL). The whole system has been simulated in MATLAB/Simulink. The settling time of estimated frequency and amplitude for proposed PLL are 0.023 and 0.024 s, respectively.

Phase locked loop (PLL) circuits are widely used in fractional frequency synthesizers. In these synthesizers, fractional multiples of the reference frequency can be synthesized, so the reference frequency and the bandwidth of the loop can be increased. This frequency synthesizer is commonly used due to its flexibility and convenient frequency adjustment. In this paper, a PLL circuit of the transistor level is designed in which a hybrid digital sigma-delta modulator with reduced hardware is used. This Digital Delta-Sigma Modulator (DDSM) has four stages that have a lower noise level and power consumption than the conventional type. This PLL circuit has a third-order loop filter and a voltage-controlled oscillator of the NMOS type. In the PLL circuit, two counters are used in its feedback path. In the proposed divider, there is a dual divider P / P + 1 (in this case 5, 6) which divides its input signal by 5, 6 according to the control input. A design example for the PLL is provided. A third stage digital Delta-Sigma modulator with reduced hardware is also used to control these counters. This modulator has less power consumption than the conventional method and has less number of transistors by 85%.

In this paper, a rotor position estimation algorithm based on sliding mode observer (SMO) and phase-locked loop (PLL) for permanent magnet synchronous motor (PMSM) control in STM32L431RCT6 microcontroller is presented. The proposed SMO and PLL-based observer has two advantages compared to the conventional SMO observer: reducing the undesirable phenomenon of chattering and improving the accuracy of rotor position estimation. In this research, a hybrid sensorless control system for PMSM drive has been designed, using the I-f startup method and a smooth transition to sensorless closed-loop vector control with SMO and PLL. C programming language is used to implement field vector control, phase-locked loop, sliding mode observer, proportional-integral controllers, space vector pulse width modulation, and coordinate transformations. The proposed method is implemented using STM32 family 32-bit microcontrollers. In the following, the presented laboratory results show the desirable performance of the proposed observer.

Phase-locked loop (PLL) is one of the most important components for the performance, control and grid synchronization of network-connected converters. The stability of PLL are affected by different factors (including the network-side and microgrid-side parameters). Similar to the effect of network-side factors, the effect of microgrid components also play an important role in the stability of PLL. The effect of the microgrid-side parameters on the stability of the PLL has not been studied so far. In this paper, using a new proposed stability criterion and with the aim of stability improvement of PLL, the optimized rate of microgrid-side and network-side Parameters is determined. First, the dynamic model of the mentioned microgrid is simulated in MATLAB software. Then, a Taguchi approach is employed in order to determine the optimal sets of microgrid-side and network-side parameters.